As transistors are scaled to smaller dimensions there is a need for higher switching speeds. One solution to increase transistor speed is to strain the silicon in the channel. Adding a small amount of strain to the silicon lattice structure is believed to promote higher electron and hole mobilities, which increase transistor drain current and device performance.
While the present invention is not limited by an particular theory, it is believed that when a silicon lattice is under tensile strain, its physical symmetry is broken, and with it the electronic symmetry. The lowest energy level of the conduction band is split, with two of the six original states dropping to a lower energy level and four rising to a higher energy level. This renders it more difficult for the electrons to be ‘scattered’ between the lowest energy states by a phonon, because there are only two states to occupy. Whenever electrons scatter, their motion is randomized. Reducing scatter increases the average distance an electron can travel before it is knocked off course, increasing its average velocity in the conduction direction. Also, distorting the lattice through tensile strain can distort the electron-lattice interaction in a way that reduces the electron's effective mass, a measure of how much it will accelerate in a given field. As a result, electron transport properties like mobility and velocity are improved and channel drive current for a given device design is increased in a strained silicon channel, leading to improved transistor performance.
Transistor strain has been generated in NMOS devices by using a highly tensile post-salicide silicon nitride capping layer on the source and drain regions. The stress from this capping layer is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in the NMOS channel. For example, a 1000 Å silicon nitride capping layer with a stress of 1E10 dynes/cm2 has been shown to provide a 10% NMOS IDSAT gain from tensile channel strain (Ghani, et al., A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors, IEEE (2003), incorporated by reference herein in its entirety for all purposes). However, a tensile stress in excess of 1E10 dynes/cm2 is necessary for optimal results.
This highly tensile silicon nitride capping layer is generally deposited using a thermal CVD process, e.g., LPCVD. However, these processes generally require temperatures of greater than 500° C. to remove hydrogen from the capping layer thereby inducing tensile stress in the capping layers, and at these higher temperatures the underlying NiSi (silicide/salicide) substrate for the capping layer undergoes phase transformation that increases its resistivity. Hence, thermal budget constraints for future transistor architectures require the films to be deposited at temperatures below 450° C. A lower temperature thermal anneal may be used, for example, one in which the anneal temperature does not exceed 450° C. However, the duration of a thermal anneal process at that temperature that is necessary to obtain the benefit (e.g., about 2 hours) is not economically viable, and neither is the stress achieved sufficiently high.
Accordingly, new fabrication processes for generating NMOS transistor channel strain are needed.